1. Field of the Invention
The present invention relates to memory circuits for use in digital computer systems and more specifically to content-addressable memory circuits.
2. Description of Prior Art
In the prior art, content-addressable memory modules (CAMMs) have been developed which perform match operations in addition to the read and write operations performed by standard memory circuits. In read and write operations, memory modules respond to addresses. In the read operation, an address is presented to the memory module and the memory module returns the data stored at that address; in the write operation, an address and data are presented to the memory module and the data is stored at the address.
In the match operation, on the other hand, an item of data is input to a CAMM, and if a matching item of data is contained in the CAMM, the CAMM indicates its location by activating a match line corresponding to the register containing the matching item of data. The degree of match required to activate the match line may be controlled by presenting a CAMM with mask bits as well as with the input data. Each mask bit corresponds to an input data bit; if the mask bit is set, the corresponding input data bit is ignored when data in the registers is compared with the item of data presented to the CAMM. Examples of such prior art CAMMs are the Intel(R) 3104, the Signetics 10155, and the Fairchild F100142. Such CAMMs are generally designed so that they may be easily combined together to form content-addressable memories (CAMs). A CAM has the same properties as a CAMM, except that a single CAM register is made up of a corresponding register from each of the CAMMs making up the CAM.
CAMs as described above may be used in digital computer systems to construct caches allowing fast access to frequently-used values by means of keys representing the values. For example, an operand in an instruction stream may contain information from which a memory address may be calculated. Once the memory address has been calculated, the memory address may be loaded into a cache and the operand may be used as a key to access the memory address in the cache. Such a cache may be constructed by combining a CAM with a fast-access memory. In the combination, each register of the fast-access memory may correspond to a register of a CAM, and a match line from the CAM register may serve to address the corresponding register of the fast-access memory. The CAM registers contain operands, and the corresponding registers of the fast-access memory contain the memory addresses corresponding to the operands. When an operand appears in the instruction stream, it is presented to the CAM. If the CAM contains the operand, the match line for the CAM register containing the operand becomes active and thereby addresses the corresponding register of the fast-access memory. The fast-access memory then responds by providing the memory address contained in the corresponding register. If the CAM does not contain the operand, a fault occurs to which the digital computer system responds by calculating the memory address represented by the operand and loading the operand into a CAM register and the memory address into the corresponding register of the fast-access memory.
The use of prior-art CAMs in applications such as that just described has been hindered by the amount of time required to clear the registers of prior-art CAMs. Such clearing is often necessary when a call or return operation is performed or when one process is removed from a processor and another loaded onto a processor. Such operations occur frequently in modern digital data processing systems, and the amount of time required to perform them has an important impact on overall system performance. In CAMs of the prior art, a register may be cleared only by performing a write operation to the register to be cleared. Thus, clearing an entire CAM requires separate write operations to each register in the CAM and clearing a CAM entry for a given operand requires presenting the operand to the CAM to obtain the address of the register containing the CAM and then performing a write operation to the register specified by the address.
The foregoing problem of the prior art and other problems as well are solved by the the invention described below.